1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and a data writing method thereof. In particular, the present invention relates to a multi-value type nonvolatile semiconductor storage device of which each memory cell stores multi-value data of two bits or more and a data writing method thereof.
2. Description of the Related Art
In recent years, flash memories are becoming common as record mediums for use with video/audio units and portable information units because of their higher electric characteristics than those of conventional various record units and hard disk units. A flash memory is a rewritable nonvolatile semiconductor storage device. With respect to connection and structure of flash memories, they can be roughly categorized as NOR type and NAND type. Conventional nonvolatile semiconductor storage devices such as memories are normally two-value type devices of which each memory cell stores data of two values "0" and "1". However, recently, as large storage capacities of semiconductor storage devices are being required, a so-called multi-value type nonvolatile semiconductor storage device of which each memory cell stores multi-value data of three values or more (two bits or more) has been proposed.
As examples of such multi-value type nonvolatile semiconductor storage devices, a four-value type NAND flash memory and an eight-value type NAND flash memory are known. In the four-value type NAND flash memory, each memory cell transistor stores data of two bits that represents four values. In the eight-value type NAND flash memory, each memory cell transistor stores data of three bits that represents eight values.
FIG. 1 is a graph showing the relation between distributions of threshold voltages Vth and data of memory cell transistors of an eight-value type NAND flash memory. In FIG. 1, the vertical axis represents threshold voltages Vth of memory cell transistors, whereas the horizontal axis represents distributions of the threshold voltages Vth of the memory cell transistors.
As shown in FIG. 1, in the eight-value type NAND flash memory, the threshold voltages Vth of the memory cell transistors are in eight states (distribution 7 to distribution 0) corresponding to data "000", "001 ", "010", "011", "100", "101", "110", and "111", respectively. In FIG. 1, VVF1, VVF2, VVF3, VVF4, VVF5, VVF6, and VVF7 represent voltages of selected word lines in verifying operations corresponding to these states. On the other hand, VRD1, VRD2, VRD3, VRD4, VRD5, VRD6, and VRD7 represent voltages of selected word lines in normal reading operations corresponding to these states. The voltages of the selected word lines have the relation of VVF7&gt;VRD7&gt;VVF6&gt;VRD6&gt;VVF5&gt;VRD5&gt;VVF4&gt;VRD4&gt;VVF3&gt;VRD3&gt;VVF2&gt;VRD2&gt;VVF1&gt;VRD1. For example, VVF7=3.8 V, VRD7=3.6 V, VVF6=3.2 V, VRD6=3.0 V, VVF5=2.6 V, VRD5=2.4 V, VVF4=2.0 V, VRD4=1.8 V, VVF3=1.4 V, VRD3=1.2 V, VVF2=0.8 V, VRD2=0.6 V, VVF1=0.2 V, VRD1=0 V.
However, in multi-value type NAND flash memories, as a method for writing data to memory cells, multi-value data is written at a time (in parallel) in such a manner that the voltage of bit lines is varied corresponding to write data. This method is referred to as multi-value parallel writing method and used to speed up the writing operations. In the case of an eight-value type NAND flash memory, ideally, as shown in column (a) of FIG. 1, when the voltage of the bit line for write data "000" is set to 0 V, the voltage of the bit line for write data "001" is set to 0.6 V, the voltage of the bit line for write data "010" is set to 1.2 V, the voltage of the bit line for write data "011" is set to 1.8 V, the voltage of the bit line for write data "100" is set to 2.4 V, the voltage of the bit line for write data "101" is set to 3.0 V, the voltage of the bit line for write data "110" is set to 3.6 V, the voltage of the bit line for write data "111" is set to 8.0 V, then all data in different write levels can be written almost at the same time.
However, from view points of low power consumption and low device area, a so-called self-boost method or local self-boost is used.
Next, with reference to FIG. 2, a self-boost writing method will be described. A memory cell of an NAND flash memory is composed of a MOS transistor having a floating gate (FG) and a control gate (CG). A predetermined number of the same memory cell transistors are connected in series as a memory string. In a memory array of the NAND flash memory, a plurality of memory strings are disposed in parallel. In the memory array, memory cell transistors on the same line are connected with a common word line. In the example shown in FIG. 2, one memory string is composed of eight memory transistors M.sub.0 to M.sub.7 connected in series. One end of the memory string (namely, the drain of a memory cell transistor M.sub.7) is connected to a bit line BL through a selected transistor DS. The other end of the memory string (the source of a memory transistor M.sub.0) is connected to a source line SL through a selected transistor SS. The control gates of the memory cell transistors M.sub.0 to M.sub.7 are connected to the word lines WL0 to WL7, respectively. The gate of the selected transistor DS is connected to a drain side selected transistor SS. The gate of the selected transistor SS is connected to a source side selected gate line SSG.
In the self-boost writing method, the signal level of the drain side selected gate line DSG is set to Vcc. In addition, the signal level of the source side selected gate line SSG is set to GND. When a memory string is selected corresponding to an address decode signal, the voltage of bit lines connected to the selected memory string is set to VBL corresponding to write data. The voltages of bit lines connected to memory strings that have not been selected are kept in a pre-charge level (i.e., in a floating state). Thereafter, the voltage of the selected word line as a write page (in this example shown in FIG. 2, the word line is WL4) is set to a predetermined write voltage VPGM. The voltage of the other non-selected word lines is set to a write pass voltage Vpass (&lt;VPGM). Thus, data is written to write memory cell transistors.
At this point, channels of memory cell transistors whose write data is the same as erase state (namely, the write data is "111") and channels of non-selected memory cell transistors of the memory string are disconnected from the relevant bit lines BL by the drain side selected transistor DS. The voltages of the memory cell transistors are boosted to a non-write voltage by a coupling connection with word lines, and mainly, non-selected word lines.
However, in the self-boost writing method or local-boost writing method, since the signal level of the drain side selected gate line DSG is set to VCC, the voltage supplied to channels of memory cell transistors of the memory string through the bit lines BL is limited to V.sub.cc --VthDSG (where VthDSG is a threshold voltage of the selected transistor DS) by the drain side selected transistor DS of the memory string. Thus, when data is written, the upper limit of the voltage supplied to the bit lines BL is V.sub.cc --VthDSG with a margin (for example, 1.5 V).
In a multi-value type NAND flash memory, from a viewpoint of a write speed, it is preferred that the voltage of bit lines is set corresponding to write data in the relation of 1 to 1. However, in an eight-value type NAND flash memory, eight-value latch circuits should be disposed corresponding to the number of bit lines. Thus, actually, the voltage of bit lines for write data "00x" (where x is 0 or 1) is set to 0 V, the voltage of bit lines for write data "01x" (where x is 0 or 1) is set to VB1, the voltage of bit lines for write data "1x" (where x is 0 or 1) is set to VB2, the voltage of bit lines for write data "110" is set to VB3, and the voltage of bit lines for write data "111" is set to V.sub.cc (where VB1, VB2, and VB3 are larger than 0 V and smaller than V.sub.cc). Thus, one voltage of a bit line is set for a plurality of pieces of data.
Thus, when data is written to an eight-value type NAND flash memory, as shown in column (b) of FIG. 2B, the voltage of bit lines for write data "00x" (where x is 0 or 1) is set to 0 V, the voltage of bit lines for write data "01x" (where x is 0 or 1) is set to 1.2 V, the voltage of bit lines for write data "10x" (where x is 0 or 1) is set to 1.5 V, the voltage of bit lines for write data "110" is set to 1.5 V, and the voltage of bit lines for write data "111" is set to V.sub.cc. In such a manner, the multi-value parallel writing operation is performed.
Next, with reference to the accompanying drawings, the structure and writing operation of an eight-value type NAND flash memory according to the multi-value parallel writing method will be described.
FIG. 3 shows principal portions of the eight-value type NAND flash memory that the inventor of the present invention has proposed. In FIG. 3, reference numeral 101 is a memory cell array. Reference numeral 102 is a bit line voltage generating circuit.
As shown in FIG. 3, a memory cell array 101 has MOS transistors (memory cell transistors) disposed in a matrix shape. Each of the MOS transistors has for example a floating gate (FG) and a control gate (CG) and functions as a three-bit memory cell. The control gates of memory cell transistors of the same lines are connected to common word lines WL0 to WL15. Memory cell transistors on the same rows are memory strings A0 to An. In FIG. 3, only the memory strings A0 and A1 are shown. The other memory strings A2 to An are omitted.
Thus, each memory string is composed of a plurality of memory cell transistors disposed in series. A memory string A0 is composed of memory cell transistors M.sub.0-0 to M.sub.15-0. The drain of the memory cell transistor M.sub.15-0 is connected to the source of a selected transistor DS0. The drain of the selected transistor DS0 is connected to a bit BL0. The source of the memory cell transistor MC.sub.0-0 is connected to the drain of a selected transistor SS0. The source of the selected transistor SS0 is connected to a source line SL. The control gates of the memory cell transistors M.sub.0-0 to M.sub.15-0 are connected to word lines WL0 to WL15, respectively. Likewise, the memory string A1 is composed of memory cell transistors M.sub.0-1 to M.sub.15-1. The drain of the memory cell transistor M.sub.15-1 is connected to the source of a selected transistor DS1. The drain of the selected transistor DS1 is connected to a bit line BL1. The source of the memory cell transistor M.sub.0-1 is connected to the drain of a selected transistor SS1. The source of the selected transistor SS1 is connected to the source line SL. The control gates of the memory cell transistors M.sub.0-1 to M.sub.15-1 are connected to the word lines WL0 to WL15, respectively.
In such a manner, the memory strings A0 and A1 are connected to various lines. These connection relations apply to the other memory strings A2 to An. Thus, first terminals of the memory strings A0 to An are connected to the bit lines BL0 to BLn through the selected transistors SS0 to SSn, respectively. The other terminals of the memory strings A0 to AN are connected to the source line SL through the selected transistors SS0 to SSn, respectively. The gates of the selected transistors DS0 to DSn are connected to a common drain side selected gate line DSG. The gates of the selected transistors SS0 to SSn are connected to a common source side selected gate line SSG. In the memory array 101, the memory strings A0 to An are disposed in parallel.
A bit line voltage generating circuit 102 is disposed corresponding to the bit lines BL0 and BL1. The bit line voltage generating circuit 102 is composed of transistors N101 to N111, latch circuits LQ2, LQ1, and LQ0, and a transistor P101. Each of the transistors N101 to N111 is composed of an n channel MOS transistor. Each of the latch circuits LQ2, LQ1, and LQ0 is composed of two invertors of which the input of the first inverter is connected to the output of the second inverter and of which the input of the second inverter is connected to the output of the first inverter. The transistor P101 is composed of a p channel MOS transistor. The bit line voltage generating circuit 102 is connected to bit line voltage supplying lines VBL1, VBL2, and VBL3 connected to respective constant voltage sources. In the NAND flash memory, two bit lines are selectively connected to the bit line voltage generating circuit 102 having the latch circuits LQ2 to LQ0. This structure is referred to as a bit line shared structure. This structure applies to other bit line voltage generating circuits corresponding to other bit lines BL2 to BLn. For simplicity, the description of the other bit line voltage generating circuits will be omitted.
The bit line voltage generating circuit 102 generates a bit line voltage corresponding to write data. The generated bit line voltage is supplied to channels of memory cell transistors of the memory cell array 101 through the bit lines BL0 to BL1.
Transistors HN101 and HN103 are connected in series between the bit BL0 and the node SA. Each of the transistors HN101 and HN103 are composed of an n channel MOS transistor with a high withstand voltage. Likewise, transistors HN102 and HN104 are connected in serial between the bit line BL1 and the node SA. Each of the transistors HN102 and HN104 is composed of an n channel MOS transistor with a high withstand voltage. A common control signal TRN is supplied to the gates of the transistors HN101 and HN102. An address decode signal AiB is supplied to the gate of the transistor HN103. An address decode signal AiN is supplied to the gate of the transistor HN104.
In the bit line voltage generating circuit 102, a transistor P101 is connected between the node SA and a power supplying line of the power supply voltage V.sub.cc (for example, V.sub.cc =3.3 V). A control signal Vref is supplied to the gate of the transistor P101. A transistor N101 is connected between the node SA and a ground line. A control signal DIS is supplied to the gate of the transistor N101.
In the bit line voltage generating circuit 102, the drain of the transistor N102 is connected to the node SA. The source of the transistor N102 is connected to the drains of the transistors N103, N105, N107, and N109. A control signal PGM is supplied to the gate of the transistor N102.
The transistors N103 and N104 are connected in series between the source of the transistor N102 and the ground line. The transistors N105 and N106 are connected in series between the source of the transistor N102 and the bit line voltage supplying line VBL1. The transistors N107 and N108 are connected in series between the source of the transistor N102 and the bit line voltage supplying line VBL2. The transistors N109, N101, and N111 are connected in series between the source of the transistor N102 and the bit line voltage supplying line VBL3.
The latch circuits LQ2, LQ1, and LQ0 have storage nodes Q2, Q1, and Q0 and their inverted storage nodes /Q2, /Q1, and /Q0, respectively (where "/" is a bar representing an inversion).
The inverted storage node /Q2 of the latch circuit LQ2 is connected to the gates of the transistors N104 and N106. The storage node Q2 of the latch circuit LQ2 is connected to the gates of the transistors N107 and N109. The inverted storage node /Q1 of the latch circuit LQ1 is connected to the gates of the transistors N103 and N108. The storage node Q1 of the latch circuit LQ1 is connected to the gates of the transistors N105 and N110. The inverted storage node /Q0 of the latch circuit LQ0 is connected to the gate of the transistor N111.
Next, with reference to a timing chart of FIG. 4, the writing operation of the eight-value type NAND flash memory will be described.
Before the writing operation is performed, the signal level of the control signal PGM is set to low (GND). Thus, the transistor N102 is turned off. Consequently, the bit lines BL0 and BL1 are disconnected from the write controlling circuit 102. The signal level of the control signal DIS is set to high (V.sub.cc). The control signal TRN and the address decode signals AiB and AiN are set to a (V.sub.cc -Vth) level. At this point, since the transistors HN101, HN102, HN103, and HN104 and the transistor N101 have been turned on, all the bit lines have been grounded. The bit line voltage supplying line VBL1 is set to VB1. The bit line voltage supplying line VBL2 is set to VB2. The bit line voltage supplying line VBL3 is set to VB3. The voltages VB1, VB2, and VB3 are higher than 0 V and lower than V.sub.cc. For example, the voltages VB1, VB2, and VB3 are 1.2 V, 1.5 V, and 1.5 V, respectively.
In such a state, when the writing operation is performed, write data is supplied to the latch circuits LQ2, LQ1, and LQ0 of the bit line voltage generating circuit 102 through the data bus. The write data is latched by the latch circuit LQ2, LQ1, and LQ1. Thereafter, the signal level of the control signal DIS is set to low. Thus, the bit lines BL0 and BL1 are disconnected from the ground line. The control signal TRN and the address decode signals AiB and AiN are set to a predetermined high level that exceeds V.sub.cc. For example, the control signal TRN and the address decode signals are set to P5 V (5 to 6 V as a path voltage when data is read). In addition, the signal level of the control signal Vref is set to low (GND). Thus, the voltages of all the bit lines are raised to V.sub.cc. Moreover, the signal level of the drain side selected gate line DSG of the memory cell array 101 is set to V.sub.cc. The signal level of the source side selected gate line SSG is set to GND. The voltage of the channel CH0 of the memory cell transistors of the memory string A0 and the voltage of the channel CHI of the memory cell transistors of the memory string A1 are raised to (V.sub.cc -VthDSG) (where VthDSG is a threshold voltage of each of the selected transistors DS0 and DS1).
Thereafter, a memory string to which data is written is selected with the address decode signals AiB and AiN. In this example, it is assumed that the memory string A0 has been selected as a memory string to which data is written. In this example, the control signal Vref is set to a predetermined voltage at which the transistor P101 allows a current necessary for compensating a leak current of the bit BL0 and so forth to flow (for example, the predetermined voltage is 2 V). In addition, the signal level of the address decode signal AiN is set to low (GND). Thus, the transistor HN104 is turned off. The non-selected side bit line BL1 is raised to V.sub.cc and kept in a floating state. The channel CH1 of the memory cell transistors of the memory string A1 is kept at (V.sub.cc -VthDSG).
After a predetermined time period elapses, the signal level of the control signal PGM is set to high. Thus, the transistor N102 is turned on. Consequently, the selected bit BL0 and the bit line voltage generating circuit 102 are connected. The selected bit BL0 is set to a voltage corresponding to the write data.
When write data is "00x" (where x is 0 or 1), the transistors N103 and N104 are turned on. Thus, a current path denoted by PATH1 shown in FIG. 3 is formed. The bit BL0 is connected to the ground line. Consequently, the voltages of the bit BL0 and the channel CH0 of the memory cell transistors of the memory string A0 are lowered to the GND level.
When the write data is "01x" (where x is 0 or 1), the transistors N105 and N106 are turned on. Thus, a current path denoted by PATH2 shown in FIG. 3 is formed. The bit BL0 is connected to the bit line voltage supplying line VBL1. Thus, the voltages of the bit BL0 and the channel CH0 of the memory cell transistors of the memory string A0 are lowered to a voltage VB1 (=1.2 V).
When the write data is "10x" (where x is 0 or 1), the transistors N107 and N108 are turned on. Thus, a current path denoted by PATH3 shown in FIG. 3 is formed. The bit line BL0 is connected to the bit line voltage supplying line VBL2. Thus, the voltages of the bit BL0 and the channel CH0 of the memory cell transistors of the memory string A0 are lowered to a voltage VB2 (=1.5 V).
When the write data is "110" (where x is 0 or 1), the transistors N109, N110, and N111 are turned on. Thus, a current path denoted by PATH4 shown in FIG. 3 is formed. The bit BL0 is connected to the bit line voltage supplying line VBL3. Thus, the voltages of the bit BL0 and the channel CH0 of the memory cell transistors of the memory string A0 are lowered to a voltage VB3 (=1.5 V).
When the write data is "111", no current path is formed. The bit BL0 is not connected to any of the ground line and the bit line supplying lines VBL1 to VBL3. Thus, the voltage of the bit BL0 is kept at V.sub.cc in a floating state. The voltage of the channel CH0 of the memory cell transistors of the memory string A0 is kept at V.sub.cc -VthDSG.
After the selected bit BL0 connected to the selected memory string A0 is set to a voltage corresponding to the write data, a selected word line for a write page of the word lines WL0 to WL15 is set to a write voltage VPGM. The other non-selected word lines are set to a write path voltage Vpss (&lt;VPGM). Thus, data is written to relevant memory cell transistors.
In memory cell transistors whose write data is not "111", Flowler-Nordheim tunneling phenomenon (hereinafter referred to as FN tunning phenomenon) takes place because of an electric field generated by a word line voltage (write voltage VPGM) supplied to the selected word line and the voltage of the channel of the memory cell transistors. Thus, data is written to the respective memory cell transistors. The channel of the memory cell transistor whose write data is "111" and the channel CH1 of the memory cell transistors of the non-selected memory string A1 are disconnected from the bit lines BL0 and BL1 by the drain side selected transistors DS0 and DS1. Because of a capacity coupling with word lines, these channels are boosted to a non-write voltage. Thus, no data is written to these memory cell transistors.
In the above-described eight-value type NAND flash memory, since write data in different write levels are written, the write time period is shorter than the case that write data in each level is written step by step.
In a NAND flash memory, when data is written, a word line voltage (as a write pulse with a predetermined pulse width) is written to a selected word line. By repeating the writing cycle, data is written to memory cells part by part. In this case, from a view point of the decrease of the number of times of the writing operation, the voltage of word lines is set to a predetermined initial voltage. Thereafter, the voltage is gradually raised with a predetermined step width. This method is referred to as ISPP (Incremental Step Pulse Programming) method.
However, in the above-described eight-value type NAND flash memory, when multi-value data is written in parallel, to prevent the memory cell transistors for write data "110" from overwriting because the difference between the ideal voltage of bit lines and the real voltage of bit lines is maximum, the voltage of a memory cell transistor that has the highest writing speed in these transistors should be set to a value so that the first writing operation causes the memory cell transistor with the highest writing speed to be in the write level. In this case, since the initial value of the voltage of the word lines is lowered by the difference between the ideal voltage of the word lines and the real voltage thereof, the electric field of a memory cell to which data whose write level is higher than that for write data "110" is written is lower than that in the ideal state. (At present time, the initial voltage in the ISPP operation is for example, 15 V. When the write data is "110", the difference between the real voltage of the bit lines and the ideal voltage thereof is 3.6 V-1.5 V 2.1 V. In this case, the ideal voltage in the initial state of the ISPP operation is around 17 V). Thus, the number of times of writing operation becomes large and thereby the write time becomes long.